Successive approximation register analog to digital converters (SAR ADCs) are among the most popular Nyquist rate ADCs because of their reasonably high conversion speed with moderate accuracy and circuit complexity. FIG. 1 illustrates the general architecture of a prior SAR ADC 100, which includes a sample and hold (S/H) circuit 102 to acquire an analog input, an analog voltage comparator 104 to compare the input to the output of a digital-to-analog converter (DAC) 106 and output the result of the comparison to a SAR 108, which is configured to provide a digital approximation of the analog input.
FIG. 2 illustrates the conceptual operation 200 of a prior SAR ADC. In the example, the analog input (represented by the horizontal dashed line) held by the sample and hold circuit (such as the S/H circuit 102 of FIG. 1) is first tested against half of the reference voltage (Vref/2) that is generated by the DAC (such as the DAC 106 of FIG. 1). Since the analog sample is higher than Vref/2, the comparator output is a 1, which is the most significant bit (MSB) of the quantized digital output and is also stored in the register SAR. The analog input sample is then tested against the DAC output (1/2+1/4)*Vref that leads to a comparator output of 0, which is the second MSB and is saved in the register SAR. This operation is repeated such that the DAC output successively approaches the true analog input sample with an accuracy that is limited only by the number of DAC bits. At the end of the conversion, the analog input is approximated by the DAC output of (1/2+0/4+0/8+0/16+1/32+1/64+0/128+1/256)*Vref, and the 8-bit digital output corresponding to the analog input sample is 1000_1101.
After the input is sampled, the conversion starts from minimum code in which all of the bits are reset to 0 except the MSB of the DAC, which is set to 1 to generate the MSB reference level. Then, the analog sample is tested against the MSB reference level to decide whether the MSB is to be kept (e.g., whether the MSB remains at 1 for the rest of the conversion cycles) or discarded (e.g., whether the MSB is reset back to 0 for the rest of the conversion cycles). This “test, keep, or discard” strategy proceeds from MSB to LSB to complete the encoding of one analog sample. Because each bit has two states due to the “keep or discard” decisions, the analog input is encoded in a binary encoding system.
In a differential implementation, which is often the choice of a high performance SAR ADC, the analog input 0 corresponds to a DAC code that generates Vref/2 as illustrated in FIG. 2, which is the mid-code of the binary encoding system. Whereas the negative peak input of a full scale signal corresponds to DAC code with all 0's, the positive peak input of a full scale signal corresponds to DAC code with all 1's.
Such prior successive approximation algorithms assume that the reference voltages generated by the DAC in every conversion cycle are accurate. In other words, any ratio error among the DAC bits will lead to signal distortion. The most effective way for a DAC to generate reference voltages with ratio matrices is through device matching, which can hardly achieve more than 12-bits of accuracy given commercial CMOS technologies. In order to design a SAR ADC with accuracy of 16-bit or higher, digital calibration techniques must be used.
The principle of digital calibration is to measure the error terms of ratios among DAC bits prior to normal SAR conversions. These error terms can be used to correct DAC outputs during normal SAR conversions (see, e.g., Hae-Seung Lee, et al., “A self-Calibrating 12b 12 μs CMOS ADC”, Proceedings of 1984 IEEE International Solid-State Circuits Conference, pp. 64-65), where the DAC needs extra analog circuitry of which the accuracy itself poses the limit of the overall conversion.
Embodiments of the invention address these and other issues in the prior art.